Generally, for a particular instruction, a microprocessor takes a certain number of clock cycles to complete its operation and produce a result. Microprocessors that implement a pipeline architecture use instruction pipelines to allow overlapping execution of multiple instructions. Processing overlapping instructions allows the microprocessor pipeline to continue execution while other pipelined instructions are being executed by various pipeline stages.
For microprocessors that use a pipeline architecture, pipelined instructions experience some amount of latency. Latency may be represented by the number of microprocessor clock cycles that occur from the time the instruction enters the instruction pipeline until the instruction generates a result. For some deterministic operations, the processing latency can be determined prior to execution of the instruction. Using the predetermined processing latency, the designer can construct an instruction pipeline to accommodate the processing latency of a particular instruction. Other types of instructions, however, do not take a data dependent amount of time to execute (i.e., no predetermined processing latency). These types of instructions, however, are typically not implemented as pipelined instructions because it is unknown when the instructions will produce a result. These limitations, in turn, reduce the processing efficiency for certain operations.